AMD triples Zen 3 CPU cache working with 3D stacking know-how

Yesterday at Computex 2021, AMD CEO Lisa Su showed off the company’s next massive performance play—3D stacked chiplets, allowing for the firm to triple the volume of L3 cache on its flagship Zen 3 CPUs.

The know-how is just what it sounds like—a layer of SRAM cache sitting down atop the Sophisticated Core Die (CCD) of the CPU alone. Present Zen 3 architecture integrates 32MiB of L3 cache for every eight-main chiplet—making 64MiB complete for a 12- or 16-core chiplet like the Ryzen 9 5900X or 5950X. The new technological know-how provides an further 64MiB L3 cache on best of each individual chiplet’s CCD, bonded with through-silicon vias (TSVs).

The further 64MiB L3 cache layer does not increase the width of the CCD, resulting in a want for structural silicon to harmony strain from the CPU cooling program. Compute and cache dies are both of those thinned in the new structure, allowing it to share substrate and warmth spreader engineering with recent Ryzen 5000 processors.

Tripling the L3 cache on Ryzen 5000 enables effectiveness gains below some workloads—particularly archive compression/decompression and gaming—similar to these seen with entire new CPU generations. AMD demonstrated efficiency uplift through a Gears of War 5 demo. Paired with an unspecified GPU and with clock speed mounted at 4 GHz, a existing-product 5900X method attained 184 fps—while the triple-cached prototype managed 206 fps, a gain of about 12 percent.

AMD promises an typical of 15 % improved gaming performance with the new technological innovation, ranging from a low of 4 percent for League of Legends to a substantial of 25 percent for Monster Hunter: Entire world. This functionality advancement calls for neither smaller method node nor improved clock speed—which is specifically attention-grabbing, in an period the place clock speeds have mostly hit a wall, and a physics-identified end to system-node shrink seems to be on the horizon as very well.

Anandtech’s Ian Cutress notes that AMD’s new 3D chiplet stacking process is plainly TSMC’s SoIC Chip-on-Wafer technology in motion. Though AMD is—at least so far—limiting itself to two layers, TSMC has shown a whole 12 levels in motion. The difficulty below is thermal—adding RAM is a around-excellent use of the technological know-how, due to the fact the extra silicon isn’t going to make much in the way of more warmth. Stacking CPU on CPU would be far extra problematic.

AMD states that the redesigned 5900X will enter generation later this year—well prior to Zen 4’s scheduled start in 2022. For now, AMD is concentrating on the new know-how for “large-stop Ryzen” CPUs only—no point out was built of Epyc, and the extra silicon needed for the added cache makes it a probably nonstarter for finances processors, provided latest supplies shortages.

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